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  1. Natarajan Somasundaram
  2. Post Doctoral research
  3. Post Doctoral research
  4. Electronics and electrical engineering
  5. Chosun University, South Korea
  6. somasundaramnatarajan@yahoo.com
  7. Download Resume
Journal Information:
Title: EAPJECT
Editor Type: Editorial Board
Bio

CAREER OBJECTIVE I aspire to pursue a highly rewarding career in both research and in academics, with challenging and healthy work environment where I can utilize my skills and knowledge efficiently for institutional growth and inspire the students to obtain leadership in my field of expertise. I believe that my technical, functional and communication skills will enable me to face the challenging career ahead. FIELDS OF SPECIALIZATION Reconfigurable Architectures, Embedded Computing Systems, VLSI Design, Fault-tolerant Systems, Image processing. CURRENT DESIGNATION Professor, Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore.

Work Background

Karpagam College of Engineering, Coimbatore, India 05/2015 – till date Professor, ECE  Taught courses for B.E. students of Electronics and Communication Engineering department and Electronics and Instrumentation Engineering department and for M.E. VLSI Design students.  Carried out industrial consultancy works. United Institute of Technology, Coimbatore, India 05/2014 – 05/2015 Professor & Dean – Electrical Sciences (R&D) / Head – R&D Centre  Taught courses for B.E. students of Electronics and Communication Engineering department and for M.E. VLSI Design and M.E. Computer Science and Engineering students.  Project Coordinator for M.E. and B.E. students.  Carried out industrial consultancy works. SSM College of Engineering, Komarapalayam, India 01/2013 – 04/2014 Professor, ECE / Research Committee Head  Taught courses for B.E. students of Electronics and Communication Engineering department and for M.E. Applied Electronics students.  Head of the Research Committee for the Institution.  Prepared the VLSI Design Laboratory manual for B.E. students of Electronics and Communication Engineering.  Project Coordinator for M.E. and B.E. students.  Carried out industrial consultancy works. Chosun University, Gwangju, South Korea 01/2012 – 04/2013 Visiting Researcher  Extended the Scalable Error Detection Coding (SEDC) algorithm for designing selfchecking ALU circuits. SSM College of Engineering, Komarapalayam, India 03/2012 – 12/2012 Associate Professor, ECE / Research Coordinator Natarajan Somasundaram - 4  Handled course on Professional Diploma in Embedded System Design in connection with MoU with OUM, Malaysia.  Taught courses for B.E. students of Electronics and Communication Engineering department and for M.E. Applied Electronics students.  Project Coordinator for M.E. and B.E. students.  Carried out industrial consultancy works. Chosun University, Gwangju, South Korea 06/2011 – 01/2012 Post Doctoral Researcher, Department of Computer Engineering / Computer Systems Lab Investigator: Dr. Jeong-A Lee  Invented the Scalable Error Detection Coding (SEDC) algorithm for designing self-checking reconfigurable circuits.  Deriving inspirations from biological cells and integrating it with SEDC algorithm for experimental design of fault-tolerant reconfigurable embedded systems. Bannari Amman Institute of Technology, Sathyamangalam, India 05/2010 – 05/2011 Assistant Professor, ECE / Professor In-charge of M.E. Embedded Systems  Taught courses for B.E. students of Electronics and Communication Engineering department and for M.E. Embedded System students.  Supervised M.E. and B.E. student projects.  Established the Embedded Design Laboratory.  Carried out industrial consultancy works.  Department Head of Industry-Institute Partnership Cell (IIPC).  Framed the M.E. Embedded System curriculum and syllabi. Sri Krishna College of Engineering and Technology, Coimbatore, India 08/2009 – 04/2010 Assistant Professor, ECE / Microprocessor and Microcontroller Laboratory  Taught courses for B.E. students of Electronics and Communication Engineering department.  Supervised B.E. student projects.  Developed course material for Microprocessor Architecture.  Executed real-time projects. Sri Krishna College of Engineering and Technology, Coimbatore, India 01/2009 – 07/2009 Senior Lecturer, ECE / Electronics Laboratory  Taught courses for B.E. students of Electronics and Communication Engineering department.  Supervised B.E. student projects.  Executed real-time projects.  Coordinated grading and labs with a team of a lecturer and a lab assistant. College of Engineering, Anna University - Chennai, India 01/2006 – 12/2008 Ph.D. Research Scholar / Senior Research Fellowship Supevisor: Dr. Y.V. Ramana Rao  Developed four new gray scale image compression algorithms.  Implemented and tested these new algorithms in FPGA. Natarajan Somasundaram - 5 Amrita Vishwa Vidyapeetham, Coimbatore, India 06/2005 – 12/2005 Lecturer, ECE / Project Coordinator of B.E. Electronics and Communication  Taught courses for B.E. students of Electronics and Communication Engineering department.  Supervised B.E. student projects. College of Engineering, Anna University - Chennai, India 07/2003 – 05/2005 Professional Assistant, ECE / Microprocessor and Microcontroller Laboratory  Supervised Microcontroller-based System Design Laboratory.  Executed real-time projects. College of Engineering, Anna University - Chennai, India 03/2002 – 06/2003 Junior Scientist Worked with Dr. A.P.J. Abdul Kalam  Partially modeled the BrainChip as a replacement for lost functionality in human brain.  Partially completed the simulation of artificially-induced dreaming.  Developed a prototype model of electronic neuron network.

Research Contributions

Journal Publications

1. V.Priyanga, V.Uma Maheswari, T.Venkatesh, S.Saravanan, P.Loganath and S.Natarajan, “Analysis of Redundant based Fault Tolerant Techniques for Embedded System”, International Journal of Applied Engineering Research, Vol. 10, No. 38, pp. 28896 – 28901, May 2015.

2. K.Tamilselvan, A.Satheesh and S.Natarajan, “Real Time kernel based Hot Spot Communication using Raspberry Pi”, International Journal for Scientific Research and Development, Vol. 3, No. 2, pp. 273 – 276, May 2015.

3. S. Natarajan and J.A. Lee, “Self-Checking Look-up Tables using Scalable Error Detection Coding (SEDC) Scheme”, Journal of Semiconductor Technology and Science, Vol. 13, No. 5, pp. 415 – 422, October 2013.

4. S. Natarajan, J.A. Lee, F. Mehdipour, N. Ramadass and Y.V. Ramana Rao, “Scalable Error Detection Coding© (SEDC) Algorithm for Totally Self-Checking (TSC) Circuits”, Consumer Electronics Times, Vol. 2, Issue 3, pp. 116 – 123, July 2013, [Special Invited Paper].

5. S. Natarajan and Y.V. Ramana Rao, “Ratio-Modified Block Truncation Coding Algorithms for Reduced Bitrates”, The Imaging Science Journal, Vol. 59, No. 1, pp. 25 – 31, February 2011. Natarajan Somasundaram - 10

6. S. Natarajan, N. Ramadass and Y.V. Ramana Rao, “State-based Dynamic Multi-Alphabet Arithmetic Coding”, The Imaging Science Journal, Vol. 57, No. 1, pp. 30 – 36, February 2009.

7. S. Natarajan and Y.V. Ramana Rao, “Modified Log-Exp based Image Compression Algorithm”, International Journal of Computer Science and Network Security, Vol. 8, No. 9, pp. 179 – 184, September 2008.

8. N. Ramadass, S. Natarajan and J. Raja Paul Perinbam, “Dynamically Reconfigurable Embedded Architecture-An Alternative to Application-Specific Digital Signal Processing Architectures”, Journal of Computer Science, Vol. 3, No. 10, pp. 823 – 828, October 2007.

9. N. Ramadass, S. Natarajan and J. Raja Paul Perinbam, “DRESPA: An Integrated System for Reconfigurable High-speed Signal Processing Applications”, International Journal of Computer Science and Network Security, Vol.7, No. 8, pp. 1 – 7, August 2007.

10. N. Ramadass, S. Natarajan and J. Raja Paul Perinbam, “Dynamically Reconfigurable (Selfmodifiable) architecture for Embedded System-on-Chip applications”, Information Technology Journal, Vol. 6, No. 1, pp. 66 – 74, January 2007.

Conference Publications

1. S. Natarajan, Farhad Mehdipour, J.A. Lee, N.Ramadass and Y.V. Ramana Rao, “Totally Self-Checking(TSC) VLSI Circuits using Scalable Error Detection Coding (SEDC) Technique”, 5 th Asian Symposium on Quality Electronic Design (asQED 2013), pp. 72 – 79, August 2013.

2. G.Revathi and S. Natarajan, “Design and Implementation of Embedded Unit for Vehicle Tracking and Automobile Accident Mitigation”, National Conference on Computer, Communication and Signal Processing (NCCCSP ‘13), pp. 49 – 52, April 2013.

3. S. Natarajan and J.A. Lee, “Scalable Error Detection Coding (SEDC) Algorithm”, US-Korea Conference on Science, Technology and Entrepreneurship (UKC2012), Poster Session, ECE-PP-19, August 2012.

4. S. Natarajan, “Bio-Inspired Reconfigurable Fault Tolerant Architecture”, progress report, 5 th Workshop on Communication Systems for Next Generation (TR-COM-11-05-KSK), 9 pages, December 2011.

5. S. Natarajan, N. Ramadass, Y.V. Ramana Rao and J. Raja Paul Perinbam, “A Non-Volatile Mixed-Signal Data Storage Cell for use in Reconfigurable Mixed-Signal System on Chip”, proc. IEEE International Conference on Industrial and Information Systems (ICIIS 2006), 5 pages, August 2006.

6. N. Ramadass, S. Natarajan, S.G. Vijaya Kumari and J. Raja Paul Perinbam, “Partially Reconfigurable (Self Modifiable) architecture using 8 bit CPU in FPGA”, proc. IEEE Natarajan Somasundaram - 11 Internationa Conference on Industrial and Information Systems (ICIIS 2006), 5 pages, August 2006.

7. N. Ramadass, G.M.A. Ibrahim, S. Natarajan and J. Raja Paul Perinbam, “Reconfigurable architecture for Algebraic codebook search”, proc. IEEE International Conference on Industrial and Information Systems (ICIIS 2006), 4 pages, August 2006.

8. S. Natarajan, N. Ramadass and Y.V. Ramana Rao, “FEMOS – A Ferroelectric MOS cell based non-volatile mixed-signal data storage for use in reconfigurable mixed-signal system-on-chip”, proc. National Conference on Trends and Developments in VLSI and Embedded Systems, 3 pages, 2006.

9. N. Ramadass, G.M.A. Ibrahim, S. Natarajan and J. Raja Paul Perinbam, “A novel architecture for modified Algebraic Code book search” proc. International Conference on Mixed Design of Integrated Circuits and System (MIXDES 2006), pp. 207 – 209, June 2006.

10. S. Natarajan and N. Ramadass, “Self-Modifiable Mixed Signal SoC Architecture for Embedded Applications”, proc. National Conference on Signals, Systems and Communications (NCSSC 2005), 5 pages, June 2005.

11. B. Sandhana, S. Natarajan and N. Ramadass, “‘Self-modifiable’ waveform generator using the PSoC Microcontroller”, proc. National Conference on Signals, Systems and Communications (NCSSC 2005), 5 pages, June 2005.

12. N.Ramadass and S.Natarajan, “Energy saving in Low Power Embedded System using Dynamic Voltage Scaling Algorithm”, proc. National Conference on Signals, Systems and Communications (NCSSC 2005), 4 pages, June 2005.

13. A. Muthamizh Selvan, S. Natarajan and N. Ramadass, “Reducing priority inversion problem in C/OS RTOS using priority inheritance protocol”, proc. National Conference on Signals, Systems and Communications (NCSSC 2005), 4 pages, June 2005.

14. S. Natarajan, N. Ramadass and J. Raja Paul Perinbam, “Design of an Embedded Computing System with Real-Time Operating System for prototyping of research and laboratory projects”, proc. National Symposium on Nuclear Instrumentation (NSNI2004), pp.607-610, January 2004.

15. S. Natarajan, N. Ramadass and J. Raja Paul Perinbam, “An Architecture for Real-Time Circuit Reconfiguration (RTCR)-based mixed-signal Reconfigurable Embedded device”, proc. International Conference on Emerging Trends (ICET 2003), 6 pages, December 2003.

16. N. Ramadass, S. Natarajan and J. Raja Paul Perinbam, “Parallel Architecture for implementation of G.729 Codec using FPGA”, proc. International Conference on Emerging Trends (ICET 2003), 5 pages, December 2003.